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| DataSheet.in UTC UC3842A / 3843A LINEAR INTEGRATED CIRCUIT CURRENT MODE PWM CONTROL CIRCUITS DESCRIPTION The UTC UC3842A/3843A provide the necessary functions to implement off-line or DC to DC fixed frequency current mode , controlled switching circuits with a minimal external part count SOP-8 FEATURES *Low external part count. *Low start up current ( Typical 0.12mA ) *Automatic feed forward compensation *Pulse-by-Pulse current limiting *Under-voltage lockout with hysteresis *Double pulse Suppression *High current totem pole output to drive MOSFET directly *Internally trimmed band gap reference *500kHz operation DIP-8 BLOCK DIAGRAM 7 Vcc Vref 8 Internal Bias 1/2Vref 5V REF S/R 5 GND Vref Good Logic 1/3Vref U.V.L.O CURRENT SENSE COMPARATOR R PWM LATCH S 7 Vcc VFB COMP 2 1 ERROR AMPLIFIER 1V 6 OUTPUT CURRENT SENSE 3 RT/CT 4 5 GND OSCILLATOR ABSOLUTE MAXIMUM RATINGS(Ta=25C) PARAMETER Supply Voltage(Low Impedance Source) Supply Voltage(Icc<30mA) Output Current ( Peak ) Output Energy(capacity Load) Analog Inputs(pin 2,3) Error Amplifier Output Sink Current Power Dissipation Lead Temperature( Soldering 10 Sec ) SYMBOL VCC Vcc Io VI(ANA) ISINK(EA) PD DIP-8 SOP-8 Tlead VALUE 30 Self Limiting +-1 5 -0.3 ~ +6.3 10 at Tamb<=25C 1.0 at Tamb<=25C 0.5 300 UNIT V V A J V mA W W C UTC UNISONIC TECHNOLOGIES CO., LTD. 1 QW-R103-002,B DataSheet.in UTC UC3842A / 3843A LINEAR INTEGRATED CIRCUIT (continued) PARAMETER Storage Temperature Operating junction temperature Note 1: Ta>25C, PD derated with 8mW/C. SYMBOL Tstg Tj VALUE -65 ~ +150 +150 UNIT C C ELECTRICAL CHARACTERISTICS (0C <=Ta<=70C,VCC=15V,RT=10k,CT=3.3nF,unless otherwise specified) PARAMETER Reference Section Output Voltage Line Regulation Load Regulation Temperature Stability Total Output Variation Output Noise Voltage Long Term Stability Output Short Circuit SYMBOL VREF VREF VREF TEST CONDITIONS Tj=25C,Io=1mA 12<=VIN<=25V 1<=Io=20mA (Note 2) Line, Load, Temp(note 2) 10Hz<=f<=10kHz,Tj=25C (note 2) Ta=25C,1000Hrs(note 2) MIN 4.9 TYP 5 6 6 0.2 50 5 -100 52 0.2 5 1.7 2.50 -0.3 90 1 70 6 -0.8 6 0.7 3 1 70 -2 150 0.1 1.5 13.5 13.5 50 50 16 8.4 10 7.6 MAX 5.1 20 25 0.4 5.18 25 -180 57 1 UNIT V mV mV mV/C V uV mV mA kHz % % V V A dB MHz dB mA mA V V V/V V dB A ns V V V V ns ns V V 4.82 Vosc ISC f f/Vcc Vosc VI(EA) IBIAS -30 Tj=25C 12<=Vcc<=25V Tmin<=TA<=Tmax(note 2) Vpin 4 peak to peak Vpin 1=2.5V 2 <=Vo<=4V Tj=25C (note 2) I2<=Vcc<=25V Vpin 2=2.7V,Vpin 1=1.1V Vpin 2=2.3V,Vpin 1=5V Vpin 2=2.3V, RL=15k to GND Vpin 2=2.7V,Vpin 1=1.1V (note 3,4) Vpin 1=5V( note 3) 12<=Vcc<=25V Vpin 3=0 to 2V 47 Oscillator Section Initial Accuracy Voltage Stability Temperature Stability Amplitude Error Amplifier Section Input Voltage Input Bias Current AVOL Unity Gain Bandwidth PSRR Output Sink Current Output Source Current Vout High Vout Low 2.42 60 0.7 60 2 -0.5 5 2.58 -2 Isink Isource VOH VOL GV VI(MAX) IBIAS 1.1 3.15 1.1 -10 300 0.4 2.2 Current Sense section Gain Maximum Input signal PSRR Input Bias Current Delay to Output 2.85 0.9 Output Section Output Low Level Output High Level Rise Time Fall Time Start Threshold Min. Operating Voltage VOL VOH tR tF VTH(ST) VOPR(min) Isink=20mA Isink=200mA Isource=20mA Isource=200mA Tj=25C,CL=1nF(note 2) Tj=25C,CL=1nF(note 2) UTC3842A UTC3843A After Turn On UTC3842A UTC3843A 13 12 150 150 17.5 9 11.5 8.2 Under-Voltage Lockout Output Section 14.5 7.8 8.5 7 V PWM Section UTC UNISONIC TECHNOLOGIES CO., LTD. 2 QW-R103-002,B DataSheet.in UTC UC3842A / 3843A LINEAR INTEGRATED CIRCUIT PARAMETER Maximum Duty Cycle Minimum Duty Cycle SYMBOL D(MAX) D(MIN) TEST CONDITIONS MIN 95 TYP 97 MAX 100 0 UNIT % % Total Standby Current Start-up Current IST Operating Supply Current ICC(opr) Vpin 2=Vpin 3=0V Vcc Zener Voltage Vz Icc=25mA note 2:These parameters, although guaranteed ,are not 100% tested in production. note 3:Parameters measured at trip point of latch with Vpin 2=0. note 4:Gain defined as: 0.12 11 34 0.3 17 mA mA V A= Vpin 1 Vpin 3 ; 0<=Vpin3<=0.8V note 5:Adjust Vcc above the start threshold before setting at 15V. OPEN-LOOP LABORATORY TEST FIXTURE Vref 4.7k RT 100k 0.1 F 1 2 8 7 6 A 0.1 F Vcc Error Amp Adjust 4.7k Isense Adjust 1k / 1W OUTPUT 3 5k 4 CT 5 High peak current associated with capacity loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin 5 in single point GND. The transistor and 5k potentio-meter are used to sample the oscillator waveform and apply an adjustable Ramp to Pin 3. UNDER-VOLTAGE LOCKOUT Icc Vcc <15mA 7 ON/OFF Command to rest of IC Von=16V Voff=10V <1mA Voff Von Vcc During Under-Voltage Lockout, the output driver is biased to a high impedance state. Pin 6 should be shunt to GND with a bleeder resistor to prevent activating the power switch with output leakage currents. UTC UNISONIC TECHNOLOGIES CO., LTD. 3 QW-R103-002,B DataSheet.in UTC UC3842A / 3843A LINEAR INTEGRATED CIRCUIT ERROR AMPLIFIER CONFIGURATION 2.5V 0.5mA Zi Zf 2 1 Error amplifier can source or sink up to 0.5mA CURRENT SENSE CIRCUIT Error Amplifier Is R 1V 2R 1 R Rs C 3 5 Current Sense Comparator Peak current (Is) determined by the formula: Ismax=10V/Rs. A small RC filter be required to suppress switch transients. SLOPE COMPENSATION 0.1 F CT 8 4 RT R1 3 R2 C Isense Rsense A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converts requiring duty cycles over 50%.Note that capacitor C, forms a filter with R2 to suppress the leading edge switch spikes. UTC UNISONIC TECHNOLOGIES CO. LTD 4 QW-R103-002,B DataSheet.in UTC UC3842A / 3843A LINEAR INTEGRATED CIRCUIT OSCILLATOR SECTION V4 8 RT Large RT Small CT INTERNAL CLOCK V4 4 CT 5 Small RT Large CT INTERNAL CLOCK Dead time VS CT(RT>5k) 100 Timing Resistance Vs Frequency 100 td (s) RT (k) CT=1nF CT=2.2nF 10 CT=4.7nF 10 CT=10nF CT=22nF 1 CT=47nF CT=100nF 1 1 10 100 10 2 0.1 10 3 10 4 10 5 10 6 CT (nF) Frequency (Hz) SHUTDOWN TECHNIQUES Shutdown UTC UC3842A can be accomplished by two methods; either raise pin 3 above 1V or pull Pin 1 below a voltage two diode drops above ground. Either method caused the output of PWM comparator to be high(refer to block diagram).The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pins 1 and/or 3 is removed . In one example, an externally latched shut -down may be accomplished by adding an SCR which be reset by cycling Vcc below the lower UVLO threshold. At this point the reference turns off allowing the SCR to reset. 1k 8 1 330 Shutdown 3 500 To current Sense resistor Shutdown UTC UNISONIC TECHNOLOGIES CO. LTD 5 QW-R103-002,B DataSheet.in UTC UC3842A / 3843A LINEAR INTEGRATED CIRCUIT TYPICAL PERFORMANCE CHARACTERISTICS 4 100 80 0 Saturation Voltage (V) Voltage Gain (dB) 3 Vcc=15V Ta=+25C Ta=-55C 2 40 -90 20 1 0 -135 -180 0 0.01 0.1 1 10 10 2 10 3 10 4 10 5 10 6 10 7 Output Current (Sourse or Sink Current) (A) Frequency (Hz) Output Saturation Characteristics Vref Temperature Drift 5.02 Error Amplifier Open-Loop Frequency Response Istart Temperature Drift 550 500 Vref (V) 5.01 Vcc=15V Io=1mA 5.00 4.99 450 Vcc=9V Istart (mA) 400 4.98 350 4.97 4.96 -50 -25 0 25 50 75 100 125 150 300 250 -50 -25 0 25 50 75 100 125 150 Temperature (C) Temperature (C) Icc Temperature Drift 15 Icc (mA) 14 Vcc=15V Io=1mA 13 12 11 10 9 -50 -25 0 25 50 75 100 125 150 Temperature (C) UTC UNISONIC TECHNOLOGIES CO. LTD 6 QW-R103-002,B PHASE (Degree) 60 -45 |
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